A Stacked Transistors CMOS SOI Power Amplifier For 5G Applications

A fifth-generation (5G) radio frequency power amplifier (PA) implemented in 45nm COMS SOI technology is presented. The design is based on a stack of six transistors divided into two cells, each with a common source and two common gate stages. The layouts of the three transistors in each cell are combined to reduce parasitic capacitances and improve the PA performance. Under 4.8 V power supply (0.8 V per transistor) and at the operating frequency of 23 GHz, the CMOS PA achieves a saturated output power (PSAT) of 18.2 dBm, a -1dB output compression power (P1dB) of 16.74 dBm and a power gain of 13.1 dB with a peak power-added efficiency (PAE) and drain efficiency (DE) of 33.9% and 40.1%, respectively. Under a larger bias voltage of 6 V (1 V per transistor), PSAT increases to 19.41 dBm while peak PAE and DE slightly reduce to 23.5% and 26.8%, respectively.