Design Procedure for Two-Stage CMOS Opamp using gm/ID design Methodology in 16 nm FinFET Technology

被引：0

作者：

Hesham, Bakr ^{[1
]}

Hasaneen, El-Sayed ^{[1
]}

Hamed, Hesham F. A. ^{[2
]}

机构：

[1] Aswan Univ, Elect Engn Dept, Aswan, Egypt

[2] Minia Univ, Elect Engn Dept, El Minia, Egypt

来源：

31ST INTERNATIONAL CONFERENCE ON MICROELECTRONICS (IEEE ICM 2019) | 2019年

关键词：

FinFET; Opamp design; gm/I-D methodology; Moderate inversion; Week inversion;

D O I：

10.1109/icm48031.2019.9021511

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper proposes a new procedure for the design of a two-stage (Miller) CMOS operational amplifier in 16 nm FinFET technology based on gm/In methodology. Unlike the conventional techniques, the proposed design flow allows the designer to reach the desired Opamp specifications from the first iteration, using pre-generated gm/I-D sizing charts, and without any need to a compact model equation for the FinFET device. The proposed procedure succeeded in describing the behavior of the FinFET device not only in strong inversion region but also in the week and moderate inversion regions. The designed Opamp is verified using 16 nm Predictive Technology Model (PTM-MG) for low-power FinFET (BSIM-CMG, level 72 technology). The results show that the proposed design methodology fulfills the desired Opamp specifications.

引用

页码：325 / 329

页数：5

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