共 50 条
- [1] Investigation on Microstructure and Resistivity in Cu-TSVs for 3D Packaging 2016 International Conference on Electronics Packaging (ICEP), 2016, : 270 - 273
- [2] Challenges in the Reliability of 3D Integration using TSVs 2015 16TH INTERNATIONAL CONFERENCE ON THERMAL, MECHANICAL AND MULTI-PHYSICS SIMULATION AND EXPERIMENTS IN MICROELECTRONICS AND MICROSYSTEMS (EUROSIME), 2015,
- [3] Oxide liner, barrier and seed layers, and Cu plating of blind through silicon vias (TSVs) on 300 mm wafers for 3D IC integration Journal of Microelectronics and Electronic Packaging, 2012, 9 (01): : 31 - 36
- [4] Electrical Investigation and Reliability of 3D Integration Platform using Cu TSVs and Micro-Bumps with Cu/Sn-BCB Hybrid Bonding 2013 IEEE 63RD ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC), 2013, : 64 - 70
- [5] Investigation of Low Temperature Cu/In Bonding in 3D Integration PROCEEDINGS OF THE 2015 IEEE INTERNATIONAL CONFERENCE ON ELECTRON DEVICES AND SOLID-STATE CIRCUITS (EDSSC), 2015, : 383 - 386
- [6] Impact of Backside Cu Contamination in the 3D integration Process 2009 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS, 2009, : 172 - 173
- [7] 3D CHIP INTEGRATION WITH THROUGH SILICON-VIAS (TSVs) PROCEEDINGS OF THE 2ND INTERNATIONAL CONFERENCE ON ADVANCED COMPUTER THEORY AND ENGINEERING (ICACTE 2009), VOLS 1 AND 2, 2009, : 1175 - 1180
- [8] Process Modeling of Dry Etching for the 3D-Integration with Tapered TSVs 2012 IEEE 62ND ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC), 2012, : 803 - 809
- [9] Low-stress TSVs for high-density 3D integration 2023 IEEE 73RD ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE, ECTC, 2023, : 606 - 611