A flexible embedded SRAM compiler

被引：0
|
作者：
Liu, Y [1 ]
Gao, ZQ [1 ]
He, XQ [1 ]
机构：
[1] Tsing Hua Univ, Inst Microelect, Beijing, Peoples R China
来源：
FIRST IEEE INTERNATION WORKSHOP ON ELECTRONIC DESIGN, TEST AND APPLICATIONS, PROCEEDINGS | 2002年
关键词：
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
SRAM Compiler uses predefined building blocks or leaf cells and connectivity information to compile SRAMs of user-specified size. In this paper, a high-speed embedded SRAM Compiler is described. It is based on TSMC's 0.5 mum CMOS process. It can compile both single-port and dual-port SRAMs. SRAM is a completely synchronous architecture with a maximal capacity 16k* 69=1Mb bits. The compiler generates the layout, behavioral level models, schematic symbols, and a layout abstraction to place and route. The program in Skill language can automatically complete the creation of all the models in different levels. The SRAM Compiler has a friendly user interface. Users can specify the necessary parameters and then get all the results. The SRAM Compiler can be easily integrated into Cadence and other CAD frameworks.
引用
收藏
页码：474 / 476
页数：3
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