Modeling and design of CMOS analog circuits through hierarchical abstraction

This paper discusses about analog circuit design methodology through hierarchical abstraction. A method of translating optimal specifications from a higher level of an hierarchy to a lower level, has been proposed. The specification-translation method has been integrated with an existing Geometric Programming based robust CMOS analog circuit sizing method. A 4th order, Sallen-Key low-pass filter has been designed using the integrated top-down design methodology targeting a 0.18 mu m technology. Total time taken to design the circuit is approximately 1.5 h. A good agreement between simulated performances of the final design with targeted specification proves efficiency of the methodology. (C) 2013 Elsevier B.V. All rights reserved.