Reconfigurable computing: design methodology and hardware tasks scheduling for real-time image processing

被引:3
作者
Kessal, Lounis [1 ]
Abel, Nicolas [1 ]
Karabernou, Si Mahmoud [1 ]
Demigny, Didier [2 ]
机构
[1] ETIS ENSEA, F-95000 Cergy, France
[2] R2D2, Lannion, France
关键词
Dynamically reconfigurable architecture; Reconfigurable SoC; Hardware tasks scheduling; Real-time image processing; IP design;
D O I
10.1007/s11554-008-0076-y
中图分类号
TP18 [人工智能理论];
学科分类号
081104 ; 0812 ; 0835 ; 1405 ;
摘要
Technology evolution makes possible the integration of heterogeneous components as programmable elements (processors), hardware dedicated blocks, hierarchical memories and buses. Furthermore, an optimized reconfigurable logic core embedded within a System-on-Chip will associate the performances of dedicated architecture and the flexibility of programmable ones. In order to increase performances, some of the applications are carried out in hardware, using dynamically reconfigurable logic, rather than software, using programmable elements. This approach offers a suitable hardware support to design malleable systems able to adapt themselves to a specific application. This article makes a synthesis of the Ardoise project. The first objective of Ardoise project was to design and to produce a dynamically reconfigurable platform based on commercial FPGAs. The concept of dynamically reconfigurable architecture depends partially on new design methodologies elaboration as well as on the programming environment. The platform architecture was designed to be suitable for real-time image processing. The article outlines mainly the Ardoise tools aspect: development environment and real-time management of the hardware tasks. The proposed methodology is based on a dynamic management of tasks according to an application scenario written using C++ language.
引用
收藏
页码:131 / 147
页数:17
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