A low-power Wave Union TDC implemented in FPGA

被引：17

作者：

Wu, J. ^{[1
]}

Shi, Y. ^{[2
]}

Zhu, D. ^{[2
]}

机构：

[1] Fermilab Natl Accelerator Lab, Batavia, IL 60510 USA

[2] Illinois Math & Sci Acad, Aurora, IL 60505 USA

来源：

JOURNAL OF INSTRUMENTATION | 2012年 / 7卷

基金：

美国能源部;

关键词：

Front-end electronics for detector readout; Digital electronic circuits;

D O I：

10.1088/1748-0221/7/01/C01021

中图分类号：

TH7 [仪器、仪表];

学科分类号：

0804 ; 080401 ; 081102 ;

摘要：

A low-power time-to-digital convertor (TDC) for an application inside a vacuum has been implemented based on the Wave Union TDC scheme in a low-cost field-programmable gate array (FPGA) device. Bench top tests have shown that a time measurement resolution better than 30 ps (standard deviation of time differences between two channels) is achieved. Special firmware design practices are taken to reduce power consumption. The measurements indicate that with 32 channels fitting in the FPGA device, the power consumption on the FPGA core voltage is approximately 9.3 mW/channel and the total power consumption including both core and I/O banks is less than 27 mW/channel.

引用

页数：9

共 14 条

[1] On the timing uncertainty in delay-line-based time measurement applications targeting FPGAs [J].