Energy-efficient design for highly associative instruction caches in next-generation embedded processors

被引：0

作者：

Aragon, JL ^{[1
]}

Nicolaescu, D ^{[1
]}

Veidenbaum, A ^{[1
]}

Badulescu, AM ^{[1
]}

机构：

[1] Univ Calif Irvine, Ctr Embedded Comp Syst, Irvine, CA 92717 USA

来源：

DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION, VOLS 1 AND 2, PROCEEDINGS | 2004年

关键词：

D O I：

10.1109/DATE.2004.1269095

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper proposes a low-energy solution for CAM-based highly associative I-caches using a segmented wordline and a predictor-based instruction fetch mechanism. Not all instructions in a given I-cache fetch are used due to branches. The proposed predictor determines which instructions in a cache access will be used and does not fetch any other instructions. Results show an average I-cache energy savings of 44% over the baseline case and 6% over the segmented case with no negative impact on performance.

引用

页码：1374 / 1375

页数：2

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