A dynamic CDMA network for multicore systems

被引:10
作者
Halak, Basel [1 ]
Ma, Teng [1 ]
Wei, Ximeng [1 ]
机构
[1] Univ Southampton, Sch Elect & Comp Engn, EEE Grp, Southampton SO9 5NH, Hants, England
关键词
Code-division multiple-access; Latency; Multicore; CHIP;
D O I
10.1016/j.mejo.2014.02.002
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Code-division multiple-access (CDMA) is a data transmission method based on the spreading code technology, wherein multiple data streams share the same physical medium with no interference. A novel architecture for on-chip communication networks based on this approach is devised. The proposed design allows sharing coding resources among network's users through the use of dynamic assignment of spreading codes. Data transmission latency is reduced by adopting a parallel structure for the coding/decoding circuitry. A 14-node CDMA network based on the proposed architecture is synthesised using 65 nm ST technology library. Performance analysis reveals that the proposed approach achieves significantly lower data packet latency compared to both conventional CDMA and packet switched network-on-chip implementations. Large area and power savings compared to existing approaches are also obtained. (C) 2014 Elsevier Ltd. All rights reserved.
引用
收藏
页码:424 / 434
页数:11
相关论文
共 16 条
  • [1] Bell Jr R. H., 2001, P 35 AS C SIGN SYST
  • [2] Xpipes: A network-on-chip architecture for gigascale systems-on-chip
    Bertozzi, Davide
    Benini, Luca
    [J]. IEEE Circuits and Systems Magazine, 2004, 4 (02) : 18 - 31
  • [3] Spreading codes for direct sequence CDMA and wideband CDMA cellular networks
    Dinan, EH
    Jabbari, B
    [J]. IEEE COMMUNICATIONS MAGAZINE, 1998, 36 (09) : 48 - 54
  • [4] Chip makers turn to multicore processors
    Geer, D
    [J]. COMPUTER, 2005, 38 (05) : 11 - 13
  • [5] AEthereal network on chip: Concepts, architectures, and implementations
    Goossens, K
    Dielissen, J
    Radulescu, A
    [J]. IEEE DESIGN & TEST OF COMPUTERS, 2005, 22 (05): : 414 - 421
  • [6] HeldJ J., 2006, FEW CORES MANY TERA
  • [7] Hennessy JL, 2019, COMPUTER ARCHITECTUR
  • [8] A 48-Core IA-32 Processor in 45 nm CMOS Using On-Die Message-Passing and DVFS for Performance and Power Scaling
    Howard, Jason
    Dighe, Saurabh
    Vangal, Sriram R.
    Ruhl, Gregory
    Borkar, Nitin
    Jain, Shailendra
    Erraguntla, Vasantha
    Konow, Michael
    Riepen, Michael
    Gries, Matthias
    Droege, Guido
    Lund-Larsen, Tor
    Steibl, Sebastian
    Borkar, Shekhar
    De, Vivek K.
    Van Der Wijngaart, Rob
    [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2011, 46 (01) : 173 - 183
  • [9] Jongsun K., 2008, IEEE T COMPUT, V57, P12
  • [10] KALLA R, 2004, IBM POWER5 CHIP DUAL