Light-weight Spiking Neuron Processing Core For Large-scale 3D-NoC Based Spiking Neural Network Processing Systems

With the increasing demand for computing machines that more closely model the biological brain, the held of neuro-inspired computing has progressed to the exploration of Spiking Neural Networks (SNN), and to best the challenges of conventional Von Neumann architecture, several hardwarebased (neuromorphic) chips have been designed. A neuromorphic chip is based on spiking neurons that process input Information only when they receive spike signals Given a sparsely-distributed input spike train, the power consumption for such event-driven hardware would be reduced since large portions of the network that are not driven by incoming spikes can be set into a powergated mode. The challenges that need to be solved toward building in hardware such a spiking neuromorphk chip with a massive number of synapse include building small-sized spiking neuro-cores with low-power consumption, efhdent neurocoding scheme, and lightweight on-chip learning algorithm. In this paper, we present the hardware implementation and evaluation of a light-weight spiking neuron processing core (SNPC) for our 3DNoC SNN processor and the design of its on-chip learning block. The SNPC embeds 256 Leaky Integrate and Fire (LIF) neurons, and crossbar based synapses, covering a chip area of 0.12mm2. Its performance is evaluated ming rdNis-r damsel, achieving an inference accuracy of 97.55%.