Analysis of evolutionary techniques for the automated implementation of digital circuits

被引：5

作者：

Zarifi, Mohammad Hossein ^{[1
]}

Satvati, Hajar ^{[2
]}

Baradaran-nia, Mehdi ^{[3
]}

机构：

[1] Univ Alberta, Dept Elect & Comp Engn, Edmonton, AB T6G 2M7, Canada

[2] Islamic Azad Univ, East Azerbaijan Sci & Res Branch, Dept Comp Engn, Tabriz, Iran

[3] Univ Tabriz, Fac Elect & Comp Engn, Dept Control Engn, Tabriz, Iran

来源：

EXPERT SYSTEMS WITH APPLICATIONS | 2015年 / 42卷 / 21期

关键词：

Evolvable Hardware; Logic circuit; Evolutionary algorithm; Genetic algorithm; HARDWARE; ALGORITHM;

D O I：

10.1016/j.eswa.2015.06.005

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

Evolvable Hardware (EHW) is hardware that can dynamically change its behavior and architecture by interacting with its environment. EHW can make use of evolutionary algorithms (EAs) to optimally synthesize electrical circuits. In this paper, five different mutation methods are implemented in a conventional genetic algorithm technique to automatically realize a digital 8 bit full adder (FA). The main achievement of this work is the comparison between those techniques in terms of number of iterations required to converge on the required logical structure. Results demonstrate that the sequential mutation method (SMM) and circular gene method (CGM) reduce the convergence time, and a substantial reduction is observed when these methods are combined with the Adaptive Group Mutation (AGM) method for the full adder implementation. (C) 2015 Elsevier Ltd. All rights reserved.

引用

页码：7620 / 7626

页数：7

共 15 条

[1] Aifeng Ren, 2011, 2011 Seventh International Conference on Natural Computation (ICNC 2011), P2112, DOI 10.1109/ICNC.2011.6022550
[2] An FPGA implementation of an Artificial Neural Network for prediction of cetane number
Alizadeh, G.
Frounchi, J.
Nia, M. Baradaran
Zarifi, M. H.
Asgarifar, S.
[J]. 2008 INTERNATIONAL CONFERENCE ON COMPUTER AND COMMUNICATION ENGINEERING, VOLS 1-3, 2008, : 605 - +
[3] A new variable topology for evolutionary hardware design
Chen, Chih-Yung
Hwang, Rey-Chue
[J]. EXPERT SYSTEMS WITH APPLICATIONS, 2009, 36 (01) : 634 - 642
[4] A genetic strategy to design cellular automata based block ciphers
Faraoun, Kamel Mohamed
[J]. EXPERT SYSTEMS WITH APPLICATIONS, 2014, 41 (17) : 7958 - 7967
[5] Kalganova T, 2000, LECT NOTES COMPUT SC, V1802, P60
[6] Nedjah N., PARALLEL EVOLUTIONAR
[7] Nia MB, 2008, INT J COMPUT SCI NET, V8, P233
[8] Speeding up the Genetic Algorithm Convergence Using Sequential Mutation and Circular Gene Methods
Nia, Mehdi Baradaran
Alipouri, Yousef
[J]. 2009 9TH INTERNATIONAL CONFERENCE ON INTELLIGENT SYSTEMS DESIGN AND APPLICATIONS, 2009, : 31 - 36
[9] A hybrid intelligent system for medical data classification
Seera, Manjeevan
Lim, Chee Peng
[J]. EXPERT SYSTEMS WITH APPLICATIONS, 2014, 41 (05) : 2239 - 2249
[10] Smith J. E., 2003, INTRO EVOLUTIONARY C

← 1 2 →