Acquisition clock dithering in a digital oscilloscope

被引：0
|
作者：
Toeppen, DE
机构：
来源：
HEWLETT-PACKARD JOURNAL | 1997年 / 48卷 / 02期
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暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
When a frequency component of the input signal is greater than half the sample rate, aliasing can occur. When the oscilloscope is equivalent time sampling, signals that are subharmonics of the sample clock will be poorly displayed. In the HP 54645A/D oscilloscopes, these effects are greatly reduced by dithering the sample clock during and between acquisitions.
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页码：26 / 28
页数：3
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