Novel CMP-based process for fabricating arrays of double-gated silicon field emitters

被引：2

作者：

Dvorson, L ^{[1
]}

Kymissis, I ^{[1
]}

Akinwande, AI ^{[1
]}

机构：

[1] MIT, Microsyst Technol Labs, Cambridge, MA 02139 USA

来源：

IVMC 2000: PROCEEDINGS OF THE 14TH INTERNATIONAL VACUUM MICROELECTRONICES CONFERENCE | 2001年

关键词：

D O I：

10.1109/IVMC.2001.939692

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Arrays of field emitters with a vertically stacked double gate were fabricated and characterized. Lowering the focus bias from 35 V to 9 V reduced spot size from 0.81 mm to 0.15 mm.

引用

页码：139 / 140

页数：2