Low power 20 Gbit/s data decision and 17 GHz static frequency divider ICs with 1.5 V supply voltage

被引:3
作者
Lao, Z
Berroth, M
Thiede, A
RiegerMotzer, M
Kaufel, G
Seibel, J
Bronner, W
Hulsmann, A
Schneider, J
Raynor, B
机构
[1] Fraunhofer-Inst. Appl. Solid-S., D-79108 Freiburg
关键词
field effect integrated circuits; frequency dividers; decision circuits;
D O I
10.1049/el:19970180
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A data decision and a static frequency divider in source coupled FET logic with a supply voltage of 1.5V have been designed and fabricated. Both circuits, using 0.2 mu m gate length enhancement and depletion AlGaAs/GaAs-HEMTs (f(T) = 60/55GHz), operate up to 20Gbit/s and 17GHz. The power consumption is 24 and 21mW for the data decision circuit and the static frequency divider together with the output buffer, respectively.
引用
收藏
页码:289 / 290
页数:2
相关论文
共 6 条
  • [1] FUJII M, 1994, IEEE GAAS IC S, P51
  • [2] E-BEAM DIRECT-WRITE IN A DRY-ETCHED RECESS GATE HEMT PROCESS FOR GAAS/ALGAAS CIRCUITS
    HULSMANN, A
    KAUFEL, G
    KOHLER, K
    RAYNOR, B
    SCHNEIDER, J
    JAKOBUS, T
    [J]. JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS, 1990, 29 (10): : 2317 - 2320
  • [3] KISHINE K, 1995, IEEE S VLSI CIRC, P127
  • [4] A NOVEL HIGH-SPEED LATCHING OPERATION FLIP-FLOP (HLO-FF) CIRCUIT AND ITS APPLICATION TO A 19-GB/S DECISION CIRCUIT USING A 0.2-MU-M GAAS-MESFET
    MURATA, K
    OTSUJI, T
    SANO, E
    OHHATA, M
    TOGASHI, M
    SUZUKI, M
    [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1995, 30 (10) : 1101 - 1108
  • [5] DESIGN TECHNIQUES FOR LOW-VOLTAGE HIGH-SPEED DIGITAL BIPOLAR CIRCUITS
    RAZAVI, B
    OTA, Y
    SWARTZ, RG
    [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1994, 29 (03) : 332 - 339
  • [6] WILHELM M, 1994, ISSCC, P94