Fractional-Order Image Edge Detector on FPGA

被引：0

作者：

Helmy, Amr H. ^{[1
]}

Ismail, Samar M. ^{[1
]}

机构：

[1] GUC, Fac IET, Cairo, Egypt

来源：

2018 30TH INTERNATIONAL CONFERENCE ON MICROELECTRONICS (ICM) | 2018年

关键词：

Edge Detection; fractional order; sliding window; floating point; image processing; FPGA;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this work, a Fractional-Order edge detector is designed and implemented. A floating point convolution unit is also presented exploiting hardware parallelism. The proposed desiy is suitable for both integer and fractional-order filters by exploiting the IEEE 754 floating point single precision representation. It also fits for different image resolutions. The design supports several tuning parameters for a greater degree of freedom in design, fractional-order parameter a, the filters used and the threshold. The system is implemented on VIRTEX 5 development board used. The maximum frequency achieved for 3 x 3 filter is 169.6 MHz.

引用

页码：339 / 342

页数：4

共 13 条

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[2]

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[3]

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