A 385 MHz 13.54 K Gates Delay Balanced Two-Level CAVLC Decoder for Ultra HD H.264/AVC Video

被引:1
作者
Liao, Yuan-Hsin [1 ]
Li, Gwo-Long [2 ]
Chang, Tian-Sheuan [3 ]
机构
[1] PixArt Imaging Inc, Hsinchu 300, Taiwan
[2] Ind Technol Res Inst, Hsinchu 302, Taiwan
[3] Natl Chiao Tung Univ, Dept Elect Engn, Hsinchu 300, Taiwan
关键词
Context-adaptive variable length decoder (CAVLD); H.264; VLSI ARCHITECTURE; DESIGN;
D O I
10.1109/TCSVT.2012.2202081
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
To satisfy the heavy performance requirement in real-time high-resolution H.264/AVC, very large-scale integrated implementation of the entropy decoder is necessary since it dominates the overall decoder throughput. In this paper, we propose a high-throughput delay balanced two-level context-based adaptive variable length coding (CAVLC) decoder with 21% shorter critical path delay in comparison to the traditional two-level decoder design. Furthermore, redundant decoding processes are removed by a skipping mechanism. The proposed CAVLC decoder only needs 127.13 cycles per macroblock on average to support level 5.1 decoding with 13.54 k gate counts under 90-nm CMOS technology.
引用
收藏
页码:1604 / 1610
页数:7
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