Enhancement-Mode GaN-Based Junctionless Vertical Surrounding-Gate Transistor with Dual-Material Gate Structure for High-Frequency Applications

被引:1
作者
Yoon, Young Jun [1 ]
Seo, Jae Hwa [1 ]
Kwon, Hyuck-In [2 ]
Lee, Jung-Hee [1 ]
Kang, In Man [1 ]
机构
[1] Kyungpook Natl Univ, Sch Elect Engn, Taegu 702701, South Korea
[2] Chung Ang Univ, Sch Elect & Elect Engn, Seoul 156756, South Korea
基金
新加坡国家研究基金会;
关键词
GaN; Junctionless Transistor; Dual-Material Gate Structure; RF Performance; THRESHOLD VOLTAGE; PERFORMANCE; NANOCHANNEL; MOSFETS; FINFETS;
D O I
10.1166/jnn.2016.13128
中图分类号
O6 [化学];
学科分类号
0703 ;
摘要
In this paper, we propose an enhancement-mode (E-mode) GaN-based junctionless field-effect transistor (FET) with a dual-material gate (DMG) structure for high-frequency performance. Its device performance is analyzed and compared with a single-material gate (SMG) device using device simulator. The DMG structure improves the drain current (I-DS) and transconductance (g(m)) because of an increase in the electron velocity in the channel region. The gate capacitance (C-gg) of the DMG structure is also decreased by reducing the gate-to-channel capacitance (C-gc) component in the gate-to-source capacitance (C-gs). Thus, the RF performance of DMG devices improves owing to the increase in g(m) and the decrease in C-gg. In addition, we examine the effect of structural variables on the performance of the DMG device. The current performance of the DMG device changes depending on the influence on the current flow in the channel region. The DMG device with an Ni-gate length (LNi-gate) of 30 nm and a smaller nanowire radius (R) enhances the maximum g(m) (g(m, max)) by increasing the effect of the DMG structure. The threshold voltage (Vth) can also be affected by LNi-gate and R. A positive Vth can be obtained by forming a channel region fully depleted by a longer LNi-gate and a smaller R. Consequently, the excellent E-mode high-frequency devices can be realized by structural optimization.
引用
收藏
页码:10204 / 10209
页数:6
相关论文
共 22 条
[1]  
[Anonymous], ATL US MAN
[2]   Scaling theory for cylindrical, fully-depleted, surrounding-gate MOSFET's [J].
Auth, CP ;
Plummer, JD .
IEEE ELECTRON DEVICE LETTERS, 1997, 18 (02) :74-76
[3]  
Baliga B. J., 1986, IEEE ELECT DEVICE L, V10, P455
[4]   Control of threshold voltage of AlGaN/GaN HEMTs by fluoride-based plasma treatment: From depletion mode to enhancement mode [J].
Cai, Yong ;
Zhou, Yugang ;
Lau, Kei May ;
Chen, Kevin J. .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2006, 53 (09) :2207-2215
[5]  
Chaudhry A, 2004, IEEE T ELECTRON DEV, V51, P1463, DOI [10.1109/TED.2004.833961, 10.1109/ted.2004.833961]
[6]   A Quasi-Two-Dimensional Threshold Voltage Model for Short-Channel Junctionless Double-Gate MOSFETs [J].
Chiang, Te-Kuang .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2012, 59 (09) :2284-2289
[7]   RF Performance and Small-Signal Parameter Extraction of Junctionless Silicon Nanowire MOSFETs [J].
Cho, Seongjae ;
Kim, Kyung Rok ;
Park, Byung-Gook ;
Kang, In Man .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2011, 58 (05) :1388-1396
[8]   Sensitivity of Threshold Voltage to Nanowire Width Variation in Junctionless Transistors [J].
Choi, Sung-Jin ;
Moon, Dong-Il ;
Kim, Sungho ;
Duarte, Juan P. ;
Choi, Yang-Kyu .
IEEE ELECTRON DEVICE LETTERS, 2011, 32 (02) :125-127
[9]   Junctionless Nanowire Transistor (JNT): Properties and design guidelines [J].
Colinge, J. P. ;
Kranti, A. ;
Yan, R. ;
Lee, C. W. ;
Ferain, I. ;
Yu, R. ;
Akhavan, N. Dehdashti ;
Razavi, P. .
SOLID-STATE ELECTRONICS, 2011, 65-66 :33-37
[10]  
Colinge JP, 2010, NAT NANOTECHNOL, V5, P225, DOI [10.1038/nnano.2010.15, 10.1038/NNANO.2010.15]