An Optimum Loop Gain Tracking All-Digital PLL Using Autocorrelation of Bang-Bang Phase-Frequency Detection

被引:36
作者
Jang, Sungchun [1 ,2 ]
Kim, Sungwoo [1 ,2 ]
Chu, Sang-Hyeok [1 ,2 ]
Jeong, Gyu-Seob [1 ,2 ]
Kim, Yoonsoo [1 ,2 ]
Jeong, Deog-Kyoon [1 ,2 ]
机构
[1] Seoul Natl Univ, Dept Elect & Comp Engn, Seoul 151742, South Korea
[2] Seoul Natl Univ, Interuniv Semicond Res Ctr, Seoul 151742, South Korea
关键词
Adaptive gain control; all-digital phase-locked loop (ADPLL); autocorrelation; bang-bang phase-frequency detector (BBPFD); bang-bang phase-locked loop (BBPLL); DESIGN; MW;
D O I
10.1109/TCSII.2015.2435691
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
An all-digital phase-locked loop with a bang-bang phase-frequency detector (BBPFD) that tracks the optimum loop gain for minimum jitter is proposed. The autocorrelation of the output of BBPFD indicates whether the bang-bang PLL operates in the nonlinear regime or the random noise regime. An adaptive loop gain controller continuously evaluates the autocorrelation of the BBPFD output and adjusts the loop gain to make the autocorrelation zero. The digital loop filter operates at higher than the reference clock frequency to reduce the loop latency and to mitigate the resolution of the digitally controlled oscillator. The prototype chip has been fabricated in a 65-nm CMOS process. The core consumes 5 mW at 2.5 GHz and exhibits root-mean-square jitter of 1.72 ps.
引用
收藏
页码:836 / 840
页数:5
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