A new ATM switch architecture: Scalable shared buffer

In this paper, a scalable shared buffer switch architecture for asynchronous transfer mode (ATM) is proposed. It has O(root N) complexity for the memory bandwidth requirement and the maximum crosspoint switch size, also O(N) scalability for buffer memory size. In this architecture, multiple buffer memories are used between the input and output side crosspoint switches. By eliminating the use of input and output time division multiplexing the new switch architecture is an improvement over the standard shared buffer approach. The proposed switch architecture is able to keep the crosspoint switches from growing as O(N-2) as is the case in the pure multibuffer architecture. It offers a good compromise between the standard shared buffer and shared multibuffer architectures. Architectural and implementation details will be discussed and a quantitative comparison between the buffer architectures will be given. Implementation of an 8 x 8 switch in 1.0 mu m CMOS technology is described.