FPGA-Based High-Performance Data Compression Deep Neural Network Accelerator

Deep neural networks play an important role in extracting valuable information from massive amounts of data. But these networks require huge computational and memory overhead, which hinders their use in resource-limited environments, such as mobile or embedded devices. In order to solve this problem, researchers usually reduce the amount of data and the number of memory accesses to reduce the overhead caused by data transmission. In this paper, we design a compressed storage and calculation fusion (CSCF) algorithm for massive input data to compress the input data volume and improve the processing efficiency of terminal equipment. Firstly, we scan and compress the collected data, then classify and store the compressed data according to the location of consecutive zero-valued pixel blocks. In order to adapt to actual development scenarios, we choose FPGA hardware architecture with high flexibility, low energy consumption, and short development cycle as the terminal processor. Therefore, we design a classification calculation unit corresponding to classification compression and storage on the FPGA architecture, and improve the performance of the model by fusing the first-layer convolution calculation of the convolution neural network and the compression storage of the input data. The evaluation results show that, compared with the traditional neural network accelerator for uncompressed transmission, our CSCF-FPGA accelerator achieves a speedup of 3.8-4.8 times on the MNIST data set and 1.8-2.1 times on the CIFAR series data set. Small fluctuations in speedup ratio and hardware resource utilization show that CSCF-FPGA not only achieves good performance, but also brings no additional hardware loss.