Investigation of 65 nm CMOS transistor local variation using a FET array

被引：16

作者：

Xu, Y. Z. ^{[1
]}

Chen, C. S. ^{[1
]}

Watt, J. T. ^{[1
]}

机构：

[1] Altera Corp, San Jose, CA 95134 USA

来源：

SOLID-STATE ELECTRONICS | 2008年 / 52卷 / 08期

关键词：

process variation; mismatch; SRAM;

D O I：

10.1016/j.sse.2008.06.002

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

CMOS FET local variation has been investigated using a new FET array structure. Key findings include four aspects. (I) At deep sub-micron technology node, local variation is significantly higher than global variation. Only 5-10% of total variation is a result of global variation. (2) Sample size affects point estimate of local variation. Sample size error can account for a significant portion of the fluctuation in the point estimate of local variation. (3) Well proximity effect (WPE) has a small impact on V, local variation. Its impact on local variation of drive current is more significant. (4) Local variation reduces with temperature. The magnitude of NMOS V-t local variation reduction is more pronounced than PMOS. These results form a solid foundation to accurately model MOSFET local variation. (C) 2008 Elsevier Ltd. All rights reserved.

引用

页码：1244 / 1248

页数：5

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