Transparent Trace-Based Binary Acceleration for Reconfigurable HW/SW Systems

被引：8

作者：

Bispo, Joao ^{[1
,2
]}

Paulino, Nuno ^{[2
,3
]}

Cardoso, Joao M. P. ^{[2
,3
]}

Ferreira, Joao C. ^{[2
,3
]}

机构：

[1] INESC ID, P-1049001 Lisbon, Portugal

[2] Univ Porto, Fac Engn, P-4200465 Oporto, Portugal

[3] INESC TEC, Inst Engn Sistemas & Comp Tecnol & Ciencia, P-4200465 Oporto, Portugal

来源：

IEEE TRANSACTIONS ON INDUSTRIAL INFORMATICS | 2013年 / 9卷 / 03期

关键词：

Binary translation; hardware accelerator; instruction traces; megablock; reconfigurable computing; ARCHITECTURE FRAMEWORK; DESIGN;

D O I：

10.1109/TII.2012.2235844

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper presents a novel approach to accelerate program execution by mapping repetitive traces of executed instructions, called Megablocks, to a runtime reconfigurable array of functional units. An offline tool suite extracts Megablocks from microprocessor instruction traces and generates a Reconfigurable Processing Unit (RPU) tailored for the execution of those Megablocks. The system is able to transparently movebcomputations from the microprocessor to the RPU at runtime. A prototype implementation of the system using a cacheless MicroBlaze microprocessor running code located in external memory reaches speedups from 2.2x to 18.2x for a set of 14 benchmark kernels. For a system setup which maximizes microprocessor performance by having the application code located in internal block RAMs, speedups from 1.4x to 2.8x were estimated.

引用

页码：1625 / 1634

页数：10

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