A low-power CMOS analog multiplier

被引：43

作者：

Chen, CH ^{[1
]}

Li, Z ^{[1
]}

机构：

[1] Univ Windsor, Dept Elect & Comp Engn, Windsor, ON N9B 3P4, Canada

来源：

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS | 2006年 / 53卷 / 02期

关键词：

analog integrated circuits; analog multipliers; CMOS; low-power design;

D O I：

10.1109/TCSII.2005.857089

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A multiplier is an important component for many analog applications. This paper presents a low power CMOS analog multiplier with performance analysis and design considerations. Experiments with SPICE simulation and results from chip testing show that this new structure has extremely low power consumption with comparable linearity and noise performance, making it very attractive for use in a variety of analog circuits.

引用

页码：100 / 104

页数：5

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