Efficient method for simulating time delays of distributed interconnections in VLSI circuits

被引：4

作者：

Maffezzoni, P ^{[1
]}

Brambilla, A ^{[1
]}

机构：

[1] Politecn Milan, Dipartimento Elettron & Informaz, I-20133 Milan, Italy

来源：

ELECTRONICS LETTERS | 1999年 / 35卷 / 12期

关键词：

D O I：

10.1049/el:19990702

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A new technique is described for modelling a general distributed RC line through a simple lumped net. This reduced order model approximates both the long time voltage response and the input loading effect of the line. The proposed method has the advantage of allowing the employment of circuit simulators such as SPICE to evaluate interconnect delays in complex layouts.

引用

页码：976 / 977

页数：2

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