An Active Test Fixture Approach for 40 Gbps and Above At-Speed Testing Using a Standard ATE System

被引：1

作者：

Moreira, Jose

Roth, Bernhard

Werkmann, Hubert

Klapproth, Lars

Howieson, Michael

Broman, Mark

Ouedraogo, Wend

Lin, Mitchell

机构：

来源：

2013 22ND ASIAN TEST SYMPOSIUM (ATS) | 2013年

关键词：

High-Speed Digital; 40; Gbps;

D O I：

10.1109/ATS.2013.57

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper presents an active test fixture approach for at-speed functional testing of high-speed I/O interfaces with automated test equipment that is able to reach data rates of 40 Gbps and above. At these data rates signal integrity is critical. Because of this we will not only discuss the solution in terms of its instrumentation but also the challenges of getting the signal to the DUT with the needed parametric performance. We will also show some results with a real application running at 40 Gbps.

引用

页码：271 / 276

页数：6

共 11 条

[1] Development of an ATE Test Cell for At-Speed Characterization and Production Testing
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[2] An approach to test compaction for scan circuits that enhances at-speed testing
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Reddy, SM
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[3] A test site thermal control system for at-speed manufacturing testing
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Maveety, J
Knostman, S
Jones, T
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Malneedi, R.
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Iyengar, V.
Lackey, D.
Grise, G.
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