A hot hole-programmed and low-temperature-formed SONOS flash memory

被引:8
|
作者
Chang, Yuan-Ming [1 ,2 ]
Yang, Wen-Luh [1 ]
Liu, Sheng-Hsien [1 ,2 ]
Hsiao, Yu-Ping [1 ,2 ]
Wu, Jia-Yo [3 ,4 ]
Wu, Chi-Chang [5 ]
机构
[1] Feng Chia Univ, Dept Elect Engn, Taichung 407, Taiwan
[2] Feng Chia Univ, PhD Program Elect & Commun Engn, Taichung 407, Taiwan
[3] Taipei Med Univ Hosp, Dept Dent, Taipei 110, Taiwan
[4] Taipei Med Univ, Sch Dent, Coll Oral Med, Taipei 110, Taiwan
[5] Taipei Med Univ, Coll Oral Med, Grad Inst Biomed Mat & Tissue Engn, Taipei 110, Taiwan
来源
NANOSCALE RESEARCH LETTERS | 2013年 / 8卷
关键词
Sol-gel; Hole trapping; Flash memory; ELECTRICAL-PROPERTIES; LAYER; TRAP; GERMANIUM;
D O I
10.1186/1556-276X-8-340
中图分类号
TB3 [工程材料学];
学科分类号
0805 ; 080502 ;
摘要
In this study, a high-performance Ti (x) Zr (y) Si (z) O flash memory is demonstrated using a sol-gel spin-coating method and formed under a low annealing temperature. The high-efficiency charge storage layer is formed by depositing a well-mixed solution of titanium tetrachloride, silicon tetrachloride, and zirconium tetrachloride, followed by 60 s of annealing at 600A degrees C. The flash memory exhibits a noteworthy hot hole trapping characteristic and excellent electrical properties regarding memory window, program/erase speeds, and charge retention. At only 6-V operation, the program/erase speeds can be as fast as 120:5.2 mu s with a 2-V shift, and the memory window can be up to 8 V. The retention times are extrapolated to 10(6) s with only 5% (at 85A degrees C) and 10% (at 125A degrees C) charge loss. The barrier height of the Ti (x) Zr (y) Si (z) O film is demonstrated to be 1.15 eV for hole trapping, through the extraction of the Poole-Frenkel current. The excellent performance of the memory is attributed to high trapping sites of the low-temperature-annealed, high-kappa sol-gel film.
引用
收藏
页数:7
相关论文
共 17 条
  • [1] A hot hole-programmed and low-temperature-formed SONOS flash memory
    Yuan-Ming Chang
    Wen-Luh Yang
    Sheng-Hsien Liu
    Yu-Ping Hsiao
    Jia-Yo Wu
    Chi-Chang Wu
    Nanoscale Research Letters, 8
  • [2] A novel SONOS nonvolatile flash memory device using substrate hot-hole injection for write and gate tunneling for erase
    Wang, Y
    Zhao, Y
    Khan, BM
    Doherty, CL
    Krayer, JD
    White, MH
    SOLID-STATE ELECTRONICS, 2004, 48 (10-11) : 2031 - 2034
  • [3] Numerical Simulation of Trapped Hole Lateral Migration and Induced Threshold Voltage Retention Loss in a SONOS Flash Memory
    Jiang, Cheng-Min
    Wu, Chih-Jung
    Wang, Tahui
    IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, 2023, 23 (01) : 147 - 152
  • [4] Low-Temperature Formed Quaternary NiZrSiGe Nanocrystal Memory
    Wu, Chia-Yu
    Huang, Huei Yu
    Wu, Chi-Chang
    INTERNATIONAL JOURNAL OF ELECTROCHEMICAL SCIENCE, 2015, 10 (08): : 6500 - 6508
  • [5] Low-temperature polycrystalline silicon thin film transistor flash memory with ferritin
    Ichikawa, Kazunori
    Uraoka, Yukiharu
    Punchaipetch, Prakaipetch
    Yano, Hiroshi
    Hatayama, Tomoaki
    Fuyuki, Takashi
    Yamashita, Ichiro
    JAPANESE JOURNAL OF APPLIED PHYSICS PART 2-LETTERS & EXPRESS LETTERS, 2007, 46 (33-35): : L804 - L806
  • [6] Profiling of nitride-trap-energy distribution in SONOS flash memory by using a variable-amplitude low-frequency charge-pumping technique
    Liao, Yi-Ying
    Horng, Sheng-Fu
    Chang, Yao-Wen
    Lu, Tao-Cheng
    Chen, Kuang-Chao
    Wang, Tahui
    Lu, Chih-Yuan
    IEEE ELECTRON DEVICE LETTERS, 2007, 28 (09) : 828 - 830
  • [7] Low-temperature polycrystalline silicon thin-film flash memory with hafnium silicate
    Lin, Yu-Hsien
    Chien, Chao-Hsin
    Chou, Tung-Huan
    Chao, Tien-Sheng
    Lei, Tan-Fu
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2007, 54 (03) : 531 - 536
  • [8] Low temperature polycrystalline silicon thin film transistors flash memory with silicon nanocrystal dot
    Ichikawa, Kazunori
    Uraoka, Yukiharu
    Yano, Hiroshi
    Hatayama, Tomoaki
    Fuyuki, Takashi
    Takahashi, Eiji
    Hayashi, Tsukasa
    Ogata, Kiyoshi
    JAPANESE JOURNAL OF APPLIED PHYSICS PART 2-LETTERS & EXPRESS LETTERS, 2007, 46 (25-28): : L661 - L663
  • [9] Forward bias enhanced channel hot electron injection for low-level programming improvement in multilevel flash memory
    Cho, CYS
    Chen, MJ
    IEICE TRANSACTIONS ON ELECTRONICS, 2004, E87C (07) : 1204 - 1207
  • [10] Batch screening of commercial serial flash-memory integrated circuits for low-temperature applications
    Ihmig, Frank R.
    Shirley, Stephen G.
    Zimmermann, Heiko
    CRYOGENICS, 2015, 71 : 39 - 46