Design and analysis of CMOS ring oscillator using 45 nm technology

被引：0
|
作者：
Sikarwar, Vandna [1 ]
Yadav, Neha [1 ]
Akashe, Shyam [2 ]
机构：
[1] ITM Univ, Gwalior, India
[2] ITM Univ, Dept E & I, Gwalior, India
来源：
PROCEEDINGS OF THE 2013 3RD IEEE INTERNATIONAL ADVANCE COMPUTING CONFERENCE (IACC) | 2013年
关键词：
CMOS; ring oscillator; power consumption; periodic steady state response (PSS);
D O I：
暂无
中图分类号：
TP301 [理论、方法];
学科分类号：
081202 ;
摘要：
This paper represents the design and analysis of ring oscillator using cadence virtuoso tool in 45 nm technology. Ring oscillator consists of odd number of stages with feedback circuit which forms a closed loop in which each stage output depends on the previous stage. In this paper, nine stage ring oscillator have been designed with a capacitor of 1 fF at each stage and simulated for various parameters such as delay, noise, jitter and power consumption. Power consumption, jitter, noise have been reduced in nine stage ring oscillator. Periodic steady state response of ring oscillator is also observed. Power consumption is reduced by 18.9 %.
引用
收藏
页码：1491 / 1495
页数：5
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