PMOS-based power-rail ESD clamp circuit with adjustable holding voltage controlled by ESD detection circuit

被引：1
|
作者：
Yeh, Chih-Ting [1 ,2 ,3 ]
Ker, Ming-Dou [2 ,3 ,4 ]
机构：
[1] Ind Technol Res Inst, Testing Engn Dept, Design Automat Technol Div, Informat & Commun Res Labs, Hsinchu, Taiwan
[2] Natl Chiao Tung Univ, Dept Elect Engn, Nanoelect & Gigascale Syst Lab, Hsinchu, Taiwan
[3] Natl Chiao Tung Univ, Inst Elect, Hsinchu 30039, Taiwan
[4] I Shou Univ, Dept Elect Engn, Kaohsiung, Taiwan
来源：
MICROELECTRONICS RELIABILITY | 2013年 / 53卷 / 02期
关键词：
DESIGN;
D O I：
10.1016/j.microrel.2012.09.016
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A new power-rail ESD clamp circuit designed with PMOS as main ESD clamp device has been proposed and verified in a 65 nm 1.2 V CMOS process. The new proposed design with adjustable holding voltage controlled by the ESD detection circuit has better immunity against mis-trigger or transient-induced latch-on event. The layout area and the standby leakage current of this new proposed design are much superior to that of traditional RC-based power-rail ESD clamp circuit with NMOS as main ESD clamp device. (C) 2012 Elsevier Ltd. All rights reserved.
引用
收藏
页码：208 / 214
页数：7
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