An Efficient Countermeasure against Fault Sensitivity Analysis Using Configurable Delay Blocks

被引:16
作者
Endo, Sho [1 ]
Li, Yang [2 ]
Homma, Naofumi [1 ]
Sakiyama, Kazuo [2 ]
Ohta, Kazuo [2 ]
Aoki, Takafumi [1 ]
机构
[1] Tohoku Univ, Grad Sch Informat Sci, Aoba Ku, 6-6-05 Aramaki Aza Aoba, Sendai, Miyagi 9808579, Japan
[2] Univ Elect Commun, Grad Sch Informat & Engn, Tokyo 1828585, Japan
来源
2012 WORKSHOP ON FAULT DIAGNOSIS AND TOLERANCE IN CRYPTOGRAPHY (FDTC) | 2012年
关键词
Fault Sensitivity Analysis; Countermeasures; Configurable delay block; AES;
D O I
10.1109/FDTC.2012.12
中图分类号
TP301 [理论、方法];
学科分类号
081202 ;
摘要
In this paper, we present an efficient countermeasure against Fault Sensitivity Analysis (FSA) based on a configurable delay blocks (CDBs). FSA is a new type of fault attack which exploits the relationship between fault sensitivity and secret information. Previous studies reported that it could break cryptographic modules equipped with conventional countermeasures against Differential Fault Analysis (DFA) such as redundancy calculation, Masked AND-OR and Wave Dynamic Differential Logic (WDDL). The proposed countermeasure can detect both DFA and FSA attacks based on setup time violation faults. The proposed ideas are to use a CDB as a time base for detection and to combine the technique with Li's countermeasure concept which removes the dependency between fault sensitivities and secret data. Post-manufacture configuration of the delay blocks allows minimization of the overhead in operating frequency which comes from manufacture variability. In this paper, we present an implementation of the proposed countermeasure, and describe its configuration method. We also investigate the hardware overhead of the proposed countermeasure implemented in ASIC for an AES module and demonstrate its validity through an experiment using a prototype FPGA implementation.
引用
收藏
页码:95 / 102
页数:8
相关论文
共 14 条
  • [1] Biham E, 1997, LECT NOTES COMPUT SC, V1294, P513
  • [2] Boneh D., 1997, Advances in Cryptology - EUROCRYPT '97. International Conference on the Theory and Application of Cryptographic Techniques Proceedings, P37
  • [3] An on-chip glitchy-clock generator for testing fault injection attacks
    Endo, Sho
    Sugawara, Takeshi
    Homma, Naofumi
    Aoki, Takafumi
    Satoh, Akashi
    [J]. JOURNAL OF CRYPTOGRAPHIC ENGINEERING, 2011, 1 (04) : 265 - 270
  • [4] Toward Effective Countermeasures against an Improved Fault Sensitivity Analysis
    Li, Yang
    Ohta, Kazuo
    Sakiyama, Kazuo
    [J]. IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, 2012, E95A (01) : 234 - 241
  • [5] Li Y, 2010, LECT NOTES COMPUT SC, V6225, P320, DOI 10.1007/978-3-642-15031-9_22
  • [6] Moradi A., 2011, COLLISION TIMING ATT
  • [7] Moradi A, 2011, LECT NOTES COMPUT SC, V6917, P292, DOI 10.1007/978-3-642-23951-9_20
  • [8] Moradi A, 2010, LECT NOTES COMPUT SC, V6225, P125, DOI 10.1007/978-3-642-15031-9_9
  • [9] Research Center for Information Security (RCIS) of National Institute of Advanced Industrial Science and Technology, SASEBO PROJ OV
  • [10] Saeki M, 2009, LECT NOTES COMPUT SC, V5747, P189