A fully integrated 4x2 element CMOS RF phased array receiver for 5G

被引:2
作者
Shaheen, Rana A. [1 ]
Akbar, Rehman [1 ]
Sethi, Alok [1 ]
Aikio, Janne P. [2 ]
Rahkonen, Timo [2 ]
Parssinen, Aarno [1 ]
机构
[1] Univ Oulu, Ctr Wireless Commun Radio Technol, POB 4500, Oulu 90014, Finland
[2] Univ Oulu, Elect Lab Circuits & Syst, POB 4500, Oulu 90014, Finland
基金
芬兰科学院;
关键词
CMOS SOI; RF; mmWave; Beamforming; Receiver; Input matching; Phased array; LNA; Phase shifter; Mixer; Vector modulator; Wireless communication; 5G;
D O I
10.1007/s10470-018-1251-0
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
This paper presents a fully integrated phased array receiver containing two four element radio frequency (RF) beamforming receivers supporting two multiple-input multiple-output channels. The receivers are designed and fabricated using 45nm CMOS SOI technology. A 10 bit IQ vector modulator phase shifter (IQVM) is implemented in RF signal paths to control the phase and amplitude of the received signal before combining. Each IQVM provides 360 degrees phase shift control and 17dB gain variation. An off-chip, simultaneous high-Q impedance matching and bandpass filtering technique for each low-noise amplifiers is presented using non-uniform transmission line segments. Measured downconversion gain at 100MHz intermediate frequency and noise figure (NF) of a single path are 23 and 5.4dB, respectively, giving estimated 3.4dB NF for a single element when simulated PCB and matching losses are taken into account. 1dB compression point and Input third-order intercept point (IIP3) are -37 and -28dBm, respectively. Each four-element receiver consumes 486mW DC power from 1.2V power supply. Total area of two receivers is 5.69mm(2).
引用
收藏
页码:429 / 440
页数:12
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