An RF Instantaneous-Hop Frequency Synthesizer based on a Zero-Initial-Phase-Error Multi-Modulus Divider

被引:0
|
作者
Chuang, Tsung-Hao [1 ]
Krishnaswamy, Harish [1 ]
机构
[1] Columbia Univ, Dept Elect Engn, New York, NY 10027 USA
来源
2014 IEEE RADIO FREQUENCY INTEGRATED CIRCUITS SYMPOSIUM | 2014年
关键词
Phase locked loops; Digital-controlled oscillators; LOCKED LOOPS;
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In this paper, we propose an instantaneous-hop frequency synthesizer based on a zero-initial-phase-error multi-modulus divider that breaks the fundamental tradeoff between hopping time, spectral purity and frequency resolution. In the proposed synthesizer, initial frequency error and phase error at the instant of hop are virtually eliminated through frequency presetting in the high-resolution voltage-controlled oscillator (VCO) and the proposed zero-initial-phase-error divider. This eliminates the acquisition process and enables "instantaneous hops" to within a frequency error that is only limited by the resolution of digital control. An IC prototype is implemented and fabricated in a standard 65nm CMOS technology. The implemented frequency synthesizer operates over 4-5.84 GHz with three discrete divider ratios (80,88,96) and achieves instantaneous hops to within an average of 3.64 MHz of the desired output frequency. The prototype dissipates 16.8 mW from 1.2V power supply.
引用
收藏
页码:433 / 436
页数:4
相关论文
共 13 条
  • [1] A 0.045-to 2.5-GHz Frequency Synthesizer with TDC-based AFC and Phase Switching Multi-Modulus Divider
    Hu, Ang
    Liu, Dongsheng
    Zhang, Kefeng
    Liu, Lanqi
    Zou, Xuecheng
    2019 IEEE 62ND INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS (MWSCAS), 2019, : 722 - 725
  • [2] A 0.045-to 2.5-GHz Frequency Synthesizer With TDC-Based AFC and Phase Switching Multi-Modulus Divider
    Hu, Ang
    Liu, Dongsheng
    Zhang, Kefeng
    Liu, Lanqi
    Zou, Xuecheng
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2020, 67 (12) : 4470 - 4483
  • [3] A 1.78–3.05 GHz fractional-N frequency synthesizer with power reduced multi-modulus divider
    Fuqing Huang
    Jianhui Wu
    Xincun Ji
    Zixuan Wang
    Meng Zhang
    Analog Integrated Circuits and Signal Processing, 2012, 72 : 97 - 109
  • [4] Analysis and optimization of seamless switching golden states of multi-modulus divider in software defined Σ-Δ Frequency synthesizer
    Hu, Ang
    Liu, Dongsheng
    Zhang, Kefeng
    MICROELECTRONICS JOURNAL, 2019, 84 : 26 - 35
  • [5] A 1.78-3.05 GHz fractional-N frequency synthesizer with power reduced multi-modulus divider
    Huang, Fuqing
    Wu, Jianhui
    Ji, Xincun
    Wang, Zixuan
    Zhang, Meng
    ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, 2012, 72 (01) : 97 - 109
  • [6] A monolithic sigma-delta fractional-N frequency synthesizer with implicit dual-path filter and phase switching multi-modulus frequency divider
    Fu, Sheng-Meng
    ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, 2007, 51 (03) : 145 - 153
  • [7] A monolithic sigma-delta fractional-N frequency synthesizer with implicit dual-path filter and phase switching multi-modulus frequency divider
    Sheng-Meng Fu
    Analog Integrated Circuits and Signal Processing, 2007, 51 : 145 - 153
  • [8] Quantization Noise Suppression in Fractional-N PLLs Utilizing Glitch-Free Phase Switching Multi-Modulus Frequency Divider
    Jin, Jing
    Liu, Xiaoming
    Mo, Tingting
    Zhou, Jianjun
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2012, 59 (05) : 926 - 937
  • [10] A 10 GHz Low-Power Multi-Modulus Frequency Divider using Extended True Single-Phase Clock (E-TSPC) Logic
    Jung, M.
    Fuhrmann, J.
    Ferizi, A.
    Fischer, G.
    Weigel, R.
    Ussmueller, T.
    2012 7TH EUROPEAN MICROWAVE INTEGRATED CIRCUITS CONFERENCE (EUMIC), 2012, : 508 - 511