Comparative Study of Full Adder Circuit with 32nm MOSFET, DG-FinFET and CNTFET

被引：0

作者：

Huq, S. M. Ishraqul ^{[1
]}

Nafreen, Maskura ^{[1
]}

Rahman, Tasnim ^{[1
]}

Bhadra, Sushovan ^{[1
]}

机构：

[1] Ahsanullah Univ Sci & Technol, Dept Elect & Elect Engn, Dhaka 1208, Bangladesh

来源：

2017 4TH INTERNATIONAL CONFERENCE ON ADVANCES IN ELECTRICAL ENGINEERING (ICAEE) | 2017年

关键词：

MOSFET; DG-FinFET; CNTFET; CMOS logic; GDI logic; power consumption; delay; PDP;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper, we study the performance of Full Adder circuit with three different FET devices, MOSFET, Double-Gate (DG) FinFET and CNTFET, in 32nm technology. The full adder circuit is implemented using two different logic styles, the conventional 28-transistor (28T) CMOS logic and Gate Diffusion Input (GDI) logic. Power consumption, delay and Power Delay Product (PDP) are investigated using LTspice and HSPICE simulations. CNTFET shows the best performance among the three with the least power consumption and delay.

引用

页码：38 / 43

页数：6

共 19 条

[1]

AbdulTahrim Aqilah binti, 2014, IEEE INT C SEM EL IC

[2]

Agarwal Lucky, 2016, IEEE INT C CONTR COM

[3]

[Anonymous], NIRM U INT C ENG NUI

[4]

[Anonymous], J COMPUTERS

[5]

[Anonymous], IEEE T ELECT DEVICES

[6] Analysis of Short Defects in FinFET Based Logic Cells [J].

Forero, Freddy ;

Galliere, Jean-Marc ;

Renovell, Michell ;

Champac, Victor .

2017 18TH IEEE LATIN AMERICAN TEST SYMPOSIUM (LATS 2017), 2017,

[7]

Jaiswal Monish, 2015, INT RES J ENG TECHNO, V2

[8]

Kaur Navneet, 2016, 2 INT INNOVATIVE APP

[9]

Klima Robert, 2002, THESIS

[10]

Mohita, 2016, 2016 IEEE STUDENTS' CONFERENCE ON ELECTRICAL, ELECTRONICS AND COMPUTER SCIENCE (SCEECS)

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