Stencil technology for wafer level bumping

被引:0
作者
Kay, Robert W. [1 ]
Cummins, Gerard [1 ]
Desmulliez, Marc P. Y. [1 ]
Krebs, Thomas [1 ]
Lathrop, Richard [1 ]
机构
[1] Univ Loughborough, Sch Mech & Mfg Engn, Addit Mfg Res Grp, Loughborough LE11 3TU, Leics, England
来源
2012 4TH ELECTRONIC SYSTEM-INTEGRATION TECHNOLOGY CONFERENCE (ESTC) | 2012年
关键词
CHALLENGES;
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Wafer level stencil printing of a Type-6 Pb-free SAC solder paste was statistically evaluated at 200 mu m and 150 mu m pitch using three different stencil manufacturing technologies: 1) laser-cut, 2) DC electroformed & 3) microengineered electroformed stencil. Factors evaluated in this study include differences between stencils in terms of printability, pitch resolution, maximum bump height achievable, print coplanarity, paste release efficiency and stencil frequency cleaning. Box plots were used to graphically view print performance over a range of aperture sizes for the three stencil types. Stencil technology impacts print performance, with the microengineered electroformed stencil producing the highest bump deposits and the lowest bump height deviation followed by the conventional electroformed and finally the laser cut stencil. Comparisons between the 1st and 5th print demonstrate consecutive printing without stencil cleaning is possible for all but the smallest spacings between apertures. High paste transfer efficiencies above 85% were achieved with the microengieered stencil using low aperture area ratios of 0.5.
引用
收藏
页数:6
相关论文
共 21 条
[1]  
Audet J., 1995, Proceedings. 1995 International Flip Chip, Ball Grid Array, TAB and Advanced Packaging Symposium, ITAP '95, P16
[2]  
Blessington D. R., 1988, U. S. Patent, Patent No. 53599281988
[3]  
Bouchoucha M, 2011, ELEC COMP C, P567, DOI 10.1109/ECTC.2011.5898568
[4]   Wafer level chip scale packaging (WL-CSP): An overview [J].
Garrou, P .
IEEE TRANSACTIONS ON ADVANCED PACKAGING, 2000, 23 (02) :198-205
[5]   Sub process challenges in ultra fine pitch stencil printing of type-6 and type-7 Pb-free solder pastes for flip chip assembly applications [J].
Jackson, GJ ;
Hendriksen, MW ;
Kay, RW ;
Desmulliez, M ;
Durairaj, RK ;
Ekere, NN .
SOLDERING & SURFACE MOUNT TECHNOLOGY, 2005, 17 (01) :24-32
[6]   Differences in the sub-processes of ultra fine pitch stencil printing due to type-6 and type-7 pb-free solder pastes used for flip chip [J].
Jackson, GJ ;
Hendriksen, MW ;
Durairaj, RK ;
Ekere, NN ;
Desmulliez, MPY ;
Kay, RW .
53RD ELECTRONIC COMPONENTS & TECHNOLOGY CONFERENCE, 2003 PROCEEDINGS, 2003, :536-543
[7]  
Jianbiao Pan, 1999, Twenty Fourth IEEE/CPMT International Electronics Manufacturing Technology Symposium (Cat. No.99CH36330), P94, DOI 10.1109/IEMT.1999.804801
[8]  
Kay R. W., 2003, U.S. Patent, Patent No. [WO20040678062003, 20040678062003]
[9]  
Kay R.W., 2003, P MICR SYST TECHN MU, P123
[10]  
Kay R. W., 2006, IMAPS DEV PACK C