A Switched-Loop-Filter PLL with Fast Phase-Error Correction Technique

被引：0

作者：

Lee, Yongsun ^{[1
]}

Seong, Taeho ^{[1
]}

Yoo, Seyeon ^{[1
]}

Choi, Jaehyouk ^{[1
]}

机构：

[1] Ulsan Natl Inst Sci & Technol, Dept Elect Engn, 50 Unist Gil, Ulsan 44919, South Korea

来源：

2018 23RD ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC) | 2018年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A low-jitter, low-reference spur switched-loop-filter (SLF) PLL that uses a fast phase-error correction (FPEC) technique emulating the phase-realignment mechanism of an injection-locked clock multiplier (ILCM) is presented. Even for a high multiplication factor (i.e., 64), the proposed SLF PLL concurrently achieved ultra-low jitter and low reference spur. The prototype was fabricated in a 65-nm CMOS process. The RMS-jitter, the FOM, and the reference spur were measured as 378 fs, -242 dB, and -71 dBc, respectively.

引用

页码：307 / 308

页数：2

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