Evaluation and Analysis of Single-Phase Clock Flip-Flops for NTV Applications

被引:0
|
作者
Cai, Yunpeng [1 ,2 ]
Savanth, Anand [1 ,2 ]
Prabhat, Pranay [2 ]
Myers, James [2 ]
Weddell, Alex S. [1 ]
Kazmierski, Tom [1 ]
机构
[1] Univ Southampton, Elect & Comp Sci, Southampton, Hants, England
[2] ARM Ltd, Cambridge, England
来源
2017 27TH INTERNATIONAL SYMPOSIUM ON POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION (PATMOS) | 2017年
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中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Performance slack in IoT applications is routinely exploited in sensor nodes to minimize power by aggressive voltage scaling. However, scaling voltage to sub-threshold levels causes severe degradation in performance and is prone to On Chip Variation (OCV). In contrast, Near Threshold Voltage (NTV) operation offers a good balance between performance loss, OCV and energy reduction and is promising for industry adoption. Unlike sub-threshold operation, where leakage power dominates, NTV designs benefit from dynamic power saving techniques, such as Single-Phase Clocked Flip-Flops (SPC FFs), which eliminate internal clock buffers. In this context, this work reviews prominent types of state-of-the-art SPC FFs and analyses their suitability for NTV operation. Five SPC FFs are reviewed and based on a preliminary analysis, two designs, which meet all NTV circuit design requirements are further investigated. These SPC FFs are designed for NTV operation in TSMC 65LP and compared against the classic transmission gate FF (TGFF). Cell-level design issues and variation are explored in the context of a 5000 gate AES encryption macro. Key design issues are identified, which erode the claimed benefits of SPC FFs when implemented as part of a larger design. We conclude that aggressive reduction in FF clock loading offers benefits but can lead to functional failures when OCV is considered, especially at NTV. Given the theoretical benefits of SPC FFs for enabling IoT, the need for further work on SPC FF designs is highlighted.
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页数:6
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