Phase-frequency detecting time-to-digital converter

被引:5
作者
Oh, D. -H. [1 ]
Choo, K. -J.
Jeong, D. -K.
机构
[1] Seoul Natl Univ, Sch Elect Engn, Seoul, South Korea
关键词
D O I
10.1049/el:20093410
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A simple time-to-digital converter (TDC), capable of detecting not only phase difference but also frequency difference, is presented. The proposed TDC guarantees pull-in even for PLLs with the lowest loop gain. The TDC is fabricated in a 65 nm CMOS process and dissipates 0.37 mW from a 1.2 V supply at 25 MHz clock frequency.
引用
收藏
页码:201 / U18
页数:2
相关论文
共 8 条
[1]   Time difference amplifier [J].
Abas, AM ;
Bystrov, A ;
Kinniment, DJ ;
Maevsky, OV ;
Russell, G ;
Yakovlev, AV .
ELECTRONICS LETTERS, 2002, 38 (23) :1437-1438
[2]   A low jitter 1.6 GHz multiplying DLL utilizing a scrambling time-to-digital converter and digital correlation [J].
Helal, Betal M. ;
Straayer, Matthew Z. ;
Wei, Gu-Yeon ;
Perrott, Michael H. .
2007 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS, 2007, :166-167
[3]  
KRATYUK V, 2006, IEEE S VLSI CIRC, P31
[4]   A 9b, 1.25 ps resolution coarse-fine time-to-digital converter in 90 nm CMOS that amplifies a time residue [J].
Lee, Minjae ;
Abidi, Asad A. .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2008, 43 (04) :769-777
[5]  
RAZAVI B, 1996, DESIGN MONOLITHIC PH, P15
[6]  
Shin J., 2007, J SEMICONDUCTOR TECH, V7, P267
[7]   1.3 V 20 ps time-to-digital converter for frequency synthesis in 90-nm CMOS [J].
Staszewski, RB ;
Vemulapalli, S ;
Vallur, P ;
Wallberg, J ;
Balsara, PT .
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2006, 53 (03) :220-224
[8]   A wide power supply range, wide tuning range, all static CMOS all digital PLL in 65 nm SOI [J].
Tierno, Jose A. ;
Rylyakov, Alexander V. ;
Friedman, Daniel J. .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2008, 43 (01) :42-51