Lin-Analyzer: A High-level Performance Analysis Tool for FPGA-based Accelerators

被引：69
|
作者：
Zhong, Guanwen [1 ]
Prakash, Alok [1 ]
Liang, Yun [2 ]
Mitra, Tulika [1 ]
Niar, Smail [3 ]
机构：
[1] Natl Univ Singapore, Sch Comp, Singapore, Singapore
[2] Peking Univ, Sch EECS, Ctr Energy Efficient Comp & Applicat, Beijing, Peoples R China
[3] Univ Valenciennes, LAMIH, Valenciennes, France
来源：
2016 ACM/EDAC/IEEE DESIGN AUTOMATION CONFERENCE (DAC) | 2016年
关键词：
D O I：
10.1145/2897937.2898040
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
The increasing complexity of FPGA-based accelerators, coupled with time-to-market pressure, makes high-level synthesis (HLS) an attractive solution to improve designer productivity by abstracting the programming effort above register-transfer level (RTL). HLS offers various architectural design options with different trade-offs via pragmas (loop unrolling, loop pipelining, array partitioning). However, non-negligible HLS runtime renders manual or automated HLS-based exhaustive architectural exploration practically infeasible. To address this challenge, we present Lin-Analyzer, a high-level accurate performance analysis tool that enables rapid design space exploration with various pragmas for FPGA-based accelerators without requiring RTL implementations.
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页数：6
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