A 65 nm 2-Billion Transistor Quad-Core Itanium Processor

被引：50

作者：

Stackhouse, Blaine ^{[1
]}

Bhimji, Sal ^{[1
]}

Bostak, Chris ^{[1
]}

Bradley, Dave ^{[1
]}

Cherkauer, Brian ^{[1
]}

Desai, Jayen ^{[1
]}

Francom, Erin ^{[1
]}

Gowan, Mike ^{[1
]}

Gronowski, Paul ^{[1
]}

Krueger, Dan ^{[1
]}

Morganti, Charles ^{[1
]}

Troyer, Steve ^{[1
]}

机构：

[1] Intel Corp, Ft Collins, CO 80528 USA

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2009年 / 44卷 / 01期

关键词：

65-nm process technology; circuit design; clock distribution; computer architecture; microprocessor; on-die cache; voltage domains; IMPLEMENTATION;

D O I：

10.1109/JSSC.2008.2007150

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper describes an Itanium processor implemented in 65 nm process with 8 layers of Cu interconnect. The 21.5 nun by 32.5 mm die has 2.05B transistors. The processor has four dual-threaded cores, 30 MB of cache, and a system interface that operates at 2.4 GHz at 105 degrees C. High speed serial interconnects allow for peak processor-to-processor bandwidth of 96 GB/s and peak memory bandwidth of 34 GB/s.

引用

页码：18 / 31

页数：14

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