Reducing variation in advanced logic technologies: Approaches to process and design for manufacturability of nanoscale CMOS

被引：199

作者：

Kuhn, Kelin J. ^{[1
]}

机构：

[1] Intel Corp, Log Technol Dev, Hillsboro, OR 97124 USA

来源：

2007 IEEE INTERNATIONAL ELECTRON DEVICES MEETING, VOLS 1 AND 2 | 2007年

关键词：

D O I：

10.1109/IEDM.2007.4418976

中图分类号：

T [工业技术];

学科分类号：

08 ;

摘要：

This paper presents an overview of process variation effects, including examples of mitigation strategies and test methods. Experimental and theoretical comparisons are presented for 45nm and 65nm RDF. SRAM matching and interconnect variation is discussed for both 65nm and 45nm, including examples of process and design mitigation strategies. Use of ring oscillators for detailed measurement of within-wafer and within-die variation is illustrated for 65nm and 45nm products.

引用

页码：471 / 474

页数：4

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