A Low Overhead Leakage Test Structure for TSVs of 3D ICs

被引:0
|
作者
Pei, Songwei [1 ]
Geng, Ye [1 ]
Jin, Yu [1 ]
机构
[1] Beijing Univ Chem Technol, Coll Informat & Technol, Beijing, Peoples R China
基金
中国国家自然科学基金;
关键词
TSV leakage test; programmable delay generator; 3D ICs;
D O I
10.1109/ICIICII.2016.76
中图分类号
TP39 [计算机的应用];
学科分类号
081203 ; 0835 ;
摘要
The through silicon via (TSV) leakage defect is one of the dominant factors that influence the yield of 3D integrated circuits (ICs). Most existing leakage test methods suffer from the narrow test range and high hardware cost. In this work, the programmable interval generator is designed for leakage test, which is revised based on LCCG. By simplification, the hardware cost of the programmable interval generator is reduced. Experimental results are presented to verify the effectiveness of the scheme.
引用
收藏
页码:166 / 169
页数:4
相关论文
共 50 条
  • [21] Coupling capacitance extraction between TSVs in 3D ICs using inverse of inductance Matrix
    Kobayashi, Tetsuya
    Niioka, Nanako
    Fukase, Masa-Aki
    Kurokawa, Atsushi
    IEEJ Transactions on Electronics, Information and Systems, 2015, 135 (07) : 744 - 751
  • [22] 3D stacked ICs using Cu TSVs and Die to Wafer Hybrid Collective bonding
    Katti, G.
    Mercha, A.
    Van Olmen, J.
    Huyghebaert, C.
    Jourdain, A.
    Stucchi, M.
    Rakowski, M.
    Debusschere, I.
    Soussan, P.
    Dehaene, W.
    De Meyer, K.
    Travaly, Y.
    Beyne, E.
    Biesemans, S.
    Swinnen, B.
    2009 IEEE INTERNATIONAL ELECTRON DEVICES MEETING, 2009, : 331 - 334
  • [23] High Aspect Ratio TSVs in Micropin-Fin Heat Sinks for 3D ICs
    Dembla, Ashish
    Zhang, Yue
    Bakir, Muhannad S.
    2012 12TH IEEE CONFERENCE ON NANOTECHNOLOGY (IEEE-NANO), 2012,
  • [24] A Segmented CA Based Approach to Test TSVs in 3D IC
    Chakraborty, Bidesh
    Dalui, Mamata
    FOURTH INTERNATIONAL CONFERENCE ON INTELLIGENT SYSTEMS, MODELLING AND SIMULATION (ISMS 2013), 2013, : 669 - 673
  • [25] Trend from ICs to 3D ICs to 3D Systems
    Tummala, Rao R.
    Sundaram, Venky
    Chatterjee, Ritwik
    Raj, P. Markondeya
    Kumbhat, Nitesh
    Sukumaran, Vijay
    Sridharan, Vivek
    Choudury, Abhishek
    Chen, Qiao
    Bandyopadhyay, Tapobrata
    PROCEEDINGS OF THE IEEE 2009 CUSTOM INTEGRATED CIRCUITS CONFERENCE, 2009, : 439 - 444
  • [26] Design Quality Tradeoff Studies for 3D ICs Built with Nano-scale TSVs and Devices
    Yang, Kaiyuan
    Kim, Dae Hyun
    Lim, Sung Kyu
    2012 13TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN (ISQED), 2012, : 740 - 746
  • [27] 3D ICs?
    不详
    INFORMACIJE MIDEM-JOURNAL OF MICROELECTRONICS ELECTRONIC COMPONENTS AND MATERIALS, 2000, 30 (02): : 123 - 123
  • [28] Layer Ordering to Minimize TSVs in Heterogeneous 3-D ICs
    Vaisband, Boris
    Friedman, Eby G.
    2016 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2016, : 1926 - 1929
  • [29] Built-in Self-prevention (BISP) for runtime ageing effects of TSVs in 3D ICs
    Maity, Dilip Kumar
    Roy, Surajit Kumar
    Giri, Chandan
    INTEGRATION-THE VLSI JOURNAL, 2024, 94
  • [30] A universal and efficient equivalent modeling method for thermal analysis of 3D ICs containing tapered TSVs
    Rao, Xixin
    Song, Jianhao
    Tian, Qing
    Liu, Huizhong
    Jin, Cheng
    Xiao, Chengdi
    INTERNATIONAL COMMUNICATIONS IN HEAT AND MASS TRANSFER, 2022, 136