A 0.032-mm2 43.3-fJ/Step 100-200-MHz IF 2-MHz Bandwidth Bandpass DSM Based on Passive N-Path Filters

被引:8
作者
Zhang, Yang [1 ]
Kinget, Peter R. [2 ]
Pun, Kong-Pang [1 ]
机构
[1] Chinese Univ Hong Kong, Dept Elect Engn, Hong Kong, Peoples R China
[2] Columbia Univ, Dept Elect Engn, New York, NY 10027 USA
关键词
Bandpass (BP) delta-sigma modulator (DSM); linear periodically time-variant (LPTV) circuit; N-path filter; power-efficient circuit and system; tunable intermediate frequency (IF); DELTA-SIGMA MODULATOR; FRONT-END; DB SNDR; MHZ; RECEIVER; CMOS; MIXERS;
D O I
10.1109/JSSC.2020.2989549
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In this article, we demonstrate a bandpass (BP) delta-sigma modulator (DSM) using passive N-path filters to implement resonators for high power efficiency, wide intermediate-frequency (IF) tuning range, and small area. The fourth-order modulator loop requires only one active element: an open-loop amplifier. The input magnitude of the amplifier is small due to the modulator's global negative feedback and the passive N-path filter preceding it. This lowers the power consumption of the amplifier and relaxes the design constraints of the switches in the N-path filter. A system model of the linear periodically time-variant structure of the proposed modulator is developed, and its nonidealities are analyzed. A BP DSM prototype realized in a 65-nm CMOS with an active area of 0.032 mm(2) features an IF tunable from 100 to 200 MHz with a sampling frequency ranging from 400 to 800 MHz. Over a fixed 2-MHz bandwidth, the modulator achieves a signal to noise and distortion ratio (SNDR) greater than 55.5 dB over the entire IF range. A maximal SNDR of 60.5 dB is achieved at 175-MHz IF while consuming 150 mu W, which corresponds to a Walden's and Schreier's figure of merits of 43.3 fJ/conv-step and 164.4 dB, respectively.
引用
收藏
页码:2443 / 2455
页数:13
相关论文
共 31 条
[1]   A 5.4 mW/0.07 mm2 2.4 GHz front-end receiver in 90 nm CMOS for IEEE 802.15.4 WPAN standard [J].
Camus, Manuel ;
Butaye, Benoit ;
Garcia, Luc ;
Sie, Mathilde ;
Pellat, Bruno ;
Parra, Thierry .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2008, 43 (06) :1372-1383
[2]   A 69 dB SNDR, 25 MHz BW, 800 MS/s Continuous-Time Bandpass ΔΣ Modulator Using a Duty-Cycle-Controlled DAC for Low Power and Reconfigurability [J].
Chae, Hyungil ;
Flynn, Michael P. .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2016, 51 (03) :649-659
[3]   A 12 mW Low Power Continuous-Time Bandpass ΔΣ Modulator With 58 dB SNDR and 24 MHz Bandwidth at 200 MHz IF [J].
Chae, Hyungil ;
Jeong, Jaehun ;
Manganaro, Gabriele ;
Flynn, Michael P. .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2014, 49 (02) :405-415
[4]   A 1-V 13-mW Single-Path Frequency-Translating ΔΣ Modulator With 55-dB SNDR and 4-MHz Bandwidth at 225 MHz [J].
Chopp, Philip M. ;
Hamoui, Anas A. .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2013, 48 (02) :473-486
[5]   An Energy-Aware CMOS Receiver Front End for Low-Power 2.4-GHz Applications [J].
Do, Aaron V. ;
Boon, Chirn Chye ;
Do, Manh Anh ;
Yeo, Kiat Seng ;
Cabuk, Alper .
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2010, 57 (10) :2675-2684
[6]   Analysis of the Signal Transfer and Folding in N-Path Filters With a Series Inductance [J].
Duipmans, Lammert ;
Struiksma, Remko E. ;
Klumperink, Eric A. M. ;
Nauta, Bram ;
van Vliet, Frank E. .
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2015, 62 (01) :263-272
[7]  
Francesconi F., 1996, ESSCIRC '96. Proceedings of the 22nd European Solid-State Circuits Conference, P216
[8]   Tunable N-Path Notch Filters for Blocker Suppression: Modeling and Verification [J].
Ghaffari, Amir ;
Klumperink, Eric A. M. ;
Nauta, Bram .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2013, 48 (06) :1370-1382
[9]  
Harrison J., 2012, IEEE ISSCC DIg. Tech. Papers, P146
[10]   A 260 MHz IF Sampling Bit-Stream Processing Digital Beamformer With an Integrated Array of Continuous-Time Band-Pass ΔΣ Modulators [J].
Jeong, Jaehun ;
Collins, Nicholas ;
Flynn, Michael P. .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2016, 51 (05) :1168-1176