Underestimation of measured self-heating in nanowires by using gate resistance technique

The channel temperature rise is demonstrated due to self-heating in narrow tri-gate fully depleted silicon-on-insulator devices becomes inaccurate when extracted using the gate resistance thermometry. Thermal resistance and channel temperature have been extracted by both gate resistance measurements and 3D TCAD electrothermal simulations for tri-gate wide and nanowire MOSFETs down to 12.5 nm fin width. A critical fin width around 500 nm the extracted channel temperature accessed by the gate resistance thermometry differs significantly from the actual channel temperature due to heat dissipation through the gate contacts is shown below, leading to significantly underestimated values.