2012 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS (APCCAS)
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2012年
关键词:
SCHEME;
D O I:
暂无
中图分类号:
TM [电工技术];
TN [电子技术、通信技术];
学科分类号:
0808 ;
0809 ;
摘要:
Scaling is often used to prevent overflow in digital signal processing (DSP). Unfortunately, scaling in residue number system (RNS) consumes significant hardware area and delay. The problem is worsened when more than one scaling factors are needed. Applications in which the computation results fall into two distinct dynamic ranges could benefit from having two scaling factors for better trade-off between precision and hardware savings. This paper presents a new unified architecture for scaling an integer in the three-moduli set {2(n)-1, 2(n), 2(n)+1} RNS by two different scaling factors, 2(n)(2(n)+1) and 2(n). The unified architecture has hardware complexity approximating the most compact adder-based RNS scaler for a single scaling constant of 2(n). Our analysis shows that the proposed dual scaler design is not only several orders of magnitude smaller but also significantly faster than the fastest LUT-based RNS scalers for the same scaling constants.
机构:
Tomsk State Pedag Univ, Dept Theoret Phys, Tomsk 634061, Russia
Natl Res Tomsk State Univ, Tomsk, RussiaTomsk State Pedag Univ, Dept Theoret Phys, Tomsk 634061, Russia
Buchbinder, I. L.
Pletnev, N. G.
论文数: 0引用数: 0
h-index: 0
机构:
Sobolev Inst Math, Dept Theoret Phys, Novosibirsk 630090, Russia
Natl Res Novosibirsk State Univ, Novosibirsk, RussiaTomsk State Pedag Univ, Dept Theoret Phys, Tomsk 634061, Russia
Pletnev, N. G.
Stepanyantz, K. V.
论文数: 0引用数: 0
h-index: 0
机构:
Moscow MV Lomonosov State Univ, Fac Phys, Dept Theoret Phys, Moscow 119991, RussiaTomsk State Pedag Univ, Dept Theoret Phys, Tomsk 634061, Russia