Impact of Variability on Processor Performance in Negative Capacitance FinFET Technology

被引:49
作者
Amrouch, Hussam [1 ]
Pahwa, Girish [2 ]
Gaidhane, Amol D. [2 ]
Dabhi, Chetan K. [2 ]
Klemme, Florian [1 ]
Prakash, Om [1 ]
Chauhan, Yogesh Singh [2 ]
机构
[1] Karlsruhe Inst Technol KIT, D-76131 Karlsruhe, Germany
[2] IIT Kanpur IITK, Kanpur 208016, Uttar Pradesh, India
关键词
FinFETs; Capacitance; Performance evaluation; Logic gates; Data models; Libraries; Negative capacitance; ferroelectric; NCFET; FinFET; process variations; reliability; processor performance; steep sub-threshold slope; VOLTAGE;
D O I
10.1109/TCSI.2020.2990672
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In this work, we investigate for the first time the impact of Negative Capacitance FinFET (NC-FinFET) technology on the performance of processors under the effects of process variations for various operating voltages. The industry compact model of FinFETs (BSIM-CMG) is fully calibrated to reproduce Intel 14nm FinFET data of high volume manufacturing process. A physics-based negative capacitance (NC) model is integrated and solved self-consistently within the BSIM-CMG model. This allows the creation of NC-FinFET standard cell libraries, while considering the effects of various variability sources both in the ferroelectric layer as well as in the underlying constituent FinFET device. The variability-aware NC-FinFET libraries, fully compatible with the existing standard design flow of circuits, are then employed to perform simulations using commercial statistical timing analysis tools in order to study the performance of a 14nm processor. For comprehensive analysis and comparisons, our implementation is done for both NC-FinFET and conventional (baseline) FinFET for a wide range of voltages. Our results demonstrate that process variations have a larger impact on the processor's performance in NC-FinFET - when it operates at a lower voltage compared to the baseline FinFET that still operates at the nominal high voltage - due to the additional ferroelectric-induced variability. Results also reveal that neglecting process variations leads to overestimating the benefit that NC brings to the processor's frequency improvement because of the larger timing guardband that is needed to overcome variability in NC-FinFET.
引用
收藏
页码:3127 / 3137
页数:11
相关论文
共 29 条
[1]   Unveiling the Impact of IR-Drop on Performance Gain in NCFET-Based Processors [J].
Amrouch, Hussam ;
Salamin, Sami ;
Pahwa, Girish ;
Gaidhane, Amol D. ;
Henkel, Joerg ;
Chauhan, Yogesh S. .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2019, 66 (07) :3215-3223
[2]   Negative Capacitance Transistor to Address the Fundamental Limitations in Technology Scaling: Processor Performance [J].
Amrouch, Hussam ;
Pahwa, Girish ;
Gaidhane, Amol D. ;
Henkel, Joerg ;
Chauhan, Yogesh Singh .
IEEE ACCESS, 2018, 6 :52754-52765
[3]  
[Anonymous], 2019, SYNOPSYS EDA SOFTWAR
[4]  
[Anonymous], 2019, CADENCE EDA SOFTWARE
[5]  
[Anonymous], 2019, SYNOPSYS EDA SOFTWAR
[6]  
[Anonymous], 2018, BSIM CMG TECHNICAL M
[7]  
Böscke TS, 2011, 2011 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM)
[8]   Intrinsic Speed Limit of Negative Capacitance Transistors [J].
Chatterjee, Korok ;
Rosner, Alexander John ;
Salahuddin, Sayeef .
IEEE ELECTRON DEVICE LETTERS, 2017, 38 (09) :1328-1330
[9]  
Chauhan Y. S., 2015, FINFET MODELING IC S, DOI [10.1016/B978-0-12-420031-9.00012-9, DOI 10.1016/B978-0-12-420031-9.00012-9]
[10]   Grain-Orientation Induced Work Function Variation in Nanoscale Metal-Gate Transistors-Part I: Modeling, Analysis, and Experimental Validation [J].
Dadgour, Hamed F. ;
Endo, Kazuhiko ;
De, Vivek K. ;
Banerjee, Kaustav .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2010, 57 (10) :2504-2514