Integrated Energy Control for Hard Real-time Networks-on-Chip

被引:2
|
作者
Kadeed, Thawra [1 ]
Tobuschat, Sebastian [1 ]
Ernst, Rolf [1 ]
机构
[1] TU Braunschweig, IDA, Braunschweig, Germany
来源
2019 IEEE 40TH REAL-TIME SYSTEMS SYMPOSIUM (RTSS 2019) | 2019年
关键词
Networks-on-Chip; Hard real-time systems; Dynamic energy management; Safe power gating; Safe clock gating; Safe DVFS; NOC; VOLTAGE;
D O I
10.1109/RTSS46320.2019.00012
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
While Networks-on-Chip (NoCs) are the prevalent solution to provide a scalable interconnect for the complex multiprocessing architectures, their associated energy consumptions have immensely increased. Specifically, hard real-time Networks-on-chip must manifest limited energy consumption as reliability issues in such a shared resource jeopardize the whole system safety. In this paper, we propose a safe and efficient approach that allows global and online energy management under temporal guarantees, i.e., all deadlines of critical functions are met. The approach introduces a control-layer to save energy on the NoC data layer through multiple Power-Aware Network Controllers (PANCs). We explore through PANCs the potential efficiency of integrating multiple energy-savings schemes in the face of the diversity of energy dissipation sources. To safely apply the PANCs in hard real-time systems while meeting the deadlines, a formal worst-case timing analysis of the additional latency induced by the control layer is provided. Experimental results demonstrate the diversity of NoC energy-savings under different combinations of energy-savings schemes. Also, the scalability of the approach is provided, inducing small area overhead.
引用
收藏
页码:4 / 16
页数:13
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