共 50 条
- [42] Security Order of Gate-Level Masking Schemes 2023 IEEE INTERNATIONAL SYMPOSIUM ON HARDWARE ORIENTED SECURITY AND TRUST, HOST, 2023, : 57 - 67
- [43] A gate-level model for morphogenetic evolvable hardware 2004 IEEE INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE TECHNOLOGY, PROCEEDINGS, 2004, : 113 - 119
- [44] Induction-based gate-level verification of multipliers ICCAD 2001: IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER AIDED DESIGN, DIGEST OF TECHNICAL PAPERS, 2001, : 190 - 193
- [45] Optimal Design on Asynchronous System with Gate-level Pipelining PROCEEDINGS OF 2015 IEEE 11TH INTERNATIONAL CONFERENCE ON ASIC (ASICON), 2015,
- [46] Gate-Level Characterization: Foundations and Hardware Security Applications PROCEEDINGS OF THE 47TH DESIGN AUTOMATION CONFERENCE, 2010, : 222 - 227
- [48] A mixed method of leakage optimization for gate-level netlist Yang, Hai-Gang, 2010, Science Press (36):
- [49] Scalable gate-level models for power and timing analysis 2007 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11, 2007, : 2938 - +
- [50] Using conjugate symmetries to enhance gate-level simulations 2006 DESIGN AUTOMATION AND TEST IN EUROPE, VOLS 1-3, PROCEEDINGS, 2006, : 636 - 641