Fan-Out RDL-first Panel-Level Packaging for Heterogeneous Integration

被引：2

作者：

Lau, John H. ^{[1
]}

Ko, Cheng-Ta ^{[1
]}

Yang, Kai-Ming ^{[1
]}

Peng, Chia-Yu ^{[1
]}

Xia, Tim ^{[1
]}

Lin, Puru Bruce ^{[1
]}

Chen, J. J. ^{[1
]}

Huang, Po-Chun ^{[1
]}

Liu, Hsing Ning ^{[1
]}

Tseng, Tzvy-Jang ^{[1
]}

机构：

[1] Unimicron Technol Corp, 179 Shanying Rd, Taoyuan 33341, Taiwan

来源：

2020 IEEE 70TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC 2020) | 2020年

关键词：

TECHNOLOGY;

D O I：

10.1109/ECTC32862.2020.00062

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this study, the fan-out chip-last panel-level packaging for heterogeneous integrations is investigated. Emphasis is placed on the design, materials, process, fabrication, and reliability of a heterogeneous integration of one large chip (10mm x 10mm) and two small chips (7mm x 5mm) by a fan-out method with a redistribution-layer (RDL)-first substrate fabricated on a 515mm x 510mm panel. Reliability assessments such as the thermal cycling of the heterogeneous integration of the 3-chip package printed circuit board (PCB) assembly are performed by a nonlinear temperature- and time-dependent finite element simulation.

引用

页码：339 / 347

页数：9

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