Test Architecture Design and Optimization for Three-Dimensional SoCs

被引：0

作者：

Jiang, Li ^{[1
]}

Huang, Lin ^{[1
]}

Xu, Qiang ^{[1
]}

机构：

[1] Chinese Univ Hong Kong, Dept Comp Sci & Engn, CUhk REliable Comp Lab CURE, Shatin, Hong Kong, Peoples R China

来源：

DATE: 2009 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION, VOLS 1-3 | 2009年

关键词：

PERFORMANCE;

D O I：

暂无

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

Core-based system-on-chips (SoCs) fabricated on three-dimensional (3D) technology are emerging for better integration capabilities. Effective test architecture design and optimization techniques are essential to minimize the manufacturing cost for such giga-scale integrated circuits. In this paper we propose novel test solutions for 3D SoCs manufactured with die-to-wafer and die-to-die bonding techniques. Both testing time and routing cost associated with the test access mechanisms in 3D SoCs are considered in our simulated annealing-based technique. Experimental results on ITC'02 SoC benchmark circuits are compared to those obtained with two baseline solutions, which show the effectiveness of the proposed technique.

引用

页码：220 / 225

页数：6

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