Robust circuit implementation of 4-bit 4-tube CNFET based ALU at 16-nm technology node

Tremendous and inescapable application of full adder adds impetus to its optimization till high-end performance. Use of full adder propels the design engineer to unearth various digital circuits, whose implementation otherwise would not be a cakewalk. This paper exhumes finest 3-bit parity checker in terms of power dissipation (PWR) and energy-delay product (EDP) variability. MCML (MOS Current Mode Logic) based implementation is practiced to improvise the circuit. Further, in this treatise, above mentioned 'CNFET-based 3-bit MCML parity checker' (used as full adder) and Transmission Gate based multiplexer is used to implement a novel design of '4-Bit 4-Tube CNFET based ALU' at 16-nm Technology Node. This CNFET-based ALU thus implemented is further compared with its CMOS counterpart. Simulation results establish the superior performance of proposed '4-Bit 4-Tube CNFET-based ALU' in terms of propagation delay (t(p)) (9.04x), PWR (1.68x), PDP (15.09x) and EDP (136.42x). The exposition establishes that the idea of using a 'CNFET-based 3-bit MCML parity checker' to design a new ALU circuit, i.e., '4-Bit 4-Tube CNFET-based ALU' would provide a gigantic horizon for a design engineer.