A 101-dB SNR Hybrid Delta-Sigma Audio ADC using Post Integration Time Control

被引：17

作者：

Choi, Moo-Yeol ^{[1
]}

Lee, Sung-No ^{[1
]}

You, Seung-Bin ^{[1
]}

Yeum, Wang-Seup ^{[1
]}

Park, Ho-Jin ^{[1
]}

Kim, Jae-Whui ^{[1
]}

Lee, Hae-Seung ^{[2
]}

机构：

[1] Samsung Elect, Yongin, South Korea

[2] MIT, Cambridge, MA 02139 USA

来源：

PROCEEDINGS OF THE IEEE 2008 CUSTOM INTEGRATED CIRCUITS CONFERENCE | 2008年

关键词：

D O I：

10.1109/CICC.2008.4672028

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A 3rd-order hybrid (continuous-time and discrete-time) delta-sigma audio ADC, implemented in 65nm CMOS process, dissipates 15mW and occupies an active die area of 0.28mm(2). A post integration time control (PITC) technique is proposed for calibration of the RC time constant variation of the continuous-time integrator. In addition, a jitter insensitive pulse generator (JIPG) circuit overcomes the degradation of SNR due to the feedback DAC clock jitter. The measured SNR and DR are 101dB and THD is -94dB.

引用

页码：89 / +

页数：2

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